1. Field
The present disclosed embodiments relate generally to computing devices, and more specifically to frequency control of multi-core processors of computing devices.
2. Background
Electronic devices, such as mobile phones, personal digital assistants (PDAs), and the like, are commonly manufactured using application specific integrated circuit (ASIC) designs. Developments in achieving high levels of silicon integration have allowed creation of complicated ASICs and field programmable gate array (FPGA) designs. These ASICs and FPGAs may be provided in a single chip to provide a system-on-a-chip (SOC). An SOC provides multiple functioning subsystems on a single semiconductor chip, such as for example, processors, multipliers, caches, and other electronic components. SOCs are particularly useful in portable electronic devices because of their integration of multiple subsystems that can provide multiple features and applications in a single chip. Further, SOCs may allow smaller portable electronic devices by use of a single chip that may otherwise have been provided using multiple chips.
To communicatively interface multiple diverse components or subsystems together within a circuit provided on a chip(s), which may be an SOC as an example, an interconnect communications bus, also referred to herein simply as a bus, is provided. The bus is provided using circuitry, including clocked circuitry, which may include as examples registers, queues, and other circuits to manage communications between the various subsystems. The circuitry in the bus is clocked with one or more clock signals generated from a master clock signal that operates at the desired bus clock frequency(ies) to provide the throughput desired.
In applications where reduced power consumption is desirable, the bus clock frequency can be lowered, but lowering the bus clock frequency lowers performance of the bus. If lowering the clock frequency of the bus increases latencies beyond latency requirements or conditions for the subsystems coupled to the bus interconnect, the performance of the subsystem may degrade or fail entirely. Rather than risk degradation or failure, the bus clock may be set to higher frequencies to reduce latency and provide performance margin, but providing a higher frequency consumes more power.
Although frequency selection based on the past load on the system bus works on some targets, trying to predict the future load based on the past load often results in making a decision regarding the selected frequency that is less than optimal.